Silicon Basis heads for FPGA test chip

Bristol startup Silicon Basis is developing a test chip for its innovative FPGA architecture that has potential to reduce the size, cost and power of a reconfigurable array to a quarter of today’s devices.

The Soft Gate Array (SGA) uses a time factor to reuse each look up table in the array and the interconnect up to eight times a cycle, dramatically reducing the size of the array and so reducing the cost to well under 25% of current FPGAs.

Although the power consumption should be the same, fine clock gating and differential signalling reduces some of that power, while the fact that logic can be kept within a single or adjacent cell dramatically reduces the power used in the interconnect.

This will reduce the power by around three quarters, says Rob Beat, CEO of Silicon Basis.

However, the array deliberately uses standard look up tables, configuration and design tools and SRAM manufacturing process to make it as standard as possible, and the time-based design elements will be added by Silicon Basis alongside the tools. This also means it will scale with process technology.

The test chip is being made by a corporate partner, and Beat is looking to develop an FPGA chip for the consumer market, as well as licensing the array for use alongside processors to make embedded chips reconfigurable or even licensing the proprietary SRAM cell.

Nick Flaherty has been covering technology and startups since 1990 and is based in Bristol, where he co-founded the SiliconSouthWest network. During that time he has worked for most of the electronics magazines and newspapers in the UK and several in Europe and the US, covering all areas of the industry. He blogs at The Embedded blog www.embeddedblog.blogspot.com and  Portable Multimedia www.portablemultimedia.blogspot.com and at www.flaherty.co.uk.