Nanowire transistors favourite to succeed finfets, says Asenov

Professor Asen Asenov

” While 16/14nm FinFETs are about to enter volume production at the major foundries, the next generation transistors suitable for 7nm CMOS and below are already on the drawing board,” says Asenov, “one of the best candidates “Gate all around” transistors, better known as nanowire transistors (NWT), have superior scaling properties compared to FinFETs and can be scaled to channel lengths of approximately 5nm. ”

With finfets the gate wraps around three of the surfaces with no gating at the bottom but, with nanowire transistors, the gate wraps all around the channel which delivers more control and less leakage.

The expected introduction of new channel materials like SiGe, Ge and III-Vs are also critical to ensure that transistor performance continues to be enhanced.

“However, this will not be a smooth ride,” warns Asenov, “the operation of CMOS transistors at 7nm and beyond is extremely complex due to strong quantum mechanical effects and quasi-ballistic transport.”

Development of such technology becomes very challenging as large combinations of transistor design parameters, channel materials and gate dielectrics need to be evaluated, a very expensive process.

Sub-optimal technology decisions could literarily bankrupt even the largest technology foundry in this $10B+ new world of CMOS technology development.

Additionally, the complexity and uncertainty of future technology also profoundly affects fabless and IP development companies, which have to prepare their designs for the new technology solutions years in advance.

“At 5nm in silicon you begin to see quantum tunnelling between the source and the drain and no one knows how to solve it,” says Asenov, “that could be the end of possible physical scaling.”

Much depends on whether they can put EUV into production. “There are so many questions and so few answers,” says Asenov, “20nm needs double patterning, 10nm will need triple or quadruple patterning which is almost prohibitive in cost. Unless they can introduce EUV economically it will be prohibitive to go any further.”

Asenov is encouraged by Intel’s order of 15 EUV machines. “It shows they are serious,” he says.

“Advanced, predictive TCAD is the answer to many of the above challenges, and there is nobody who can provide better, silicon proven, tools for these purposes than GSS,” says Asenov, “the beyond the state-of-the-art GSS ‘atomistic’ simulator GARAND can predict the characteristics of NWT, including quantum mechanical & non-equilibrium transport effects as well as global and local variability.”

“The best in class quantum simulation and correction technologies accurately capture the impact of quantum effects on the performance of NWTs,” adds Asenov, “the ensemble Monte Carlo (EMC) transport module of GARAND, which includes multi sub-band EMC, predicts accurately the performance of these future devices based on the electronic properties of different channel materials. These tools allow fast screening of future technology options and ensures that the right technology decisions are made as early as possible in the development cycle.”

Once decisions are made, the GSS design-technology co-optimisation (DTCO) tool chain allows fast development of accurate early PDKs. This facilitates fabless companies in making the best technology choice according to their specific product requirements. Once the technology is chosen it can then be optimised for particular applications using the automated GSS DTCO tool chain, giving an invaluable differentiator within a highly competitive market.

“The GSS TCAD toolchain can significantly reduce the cost and risk associated with making the right decisions when moving to NWT CMOS technology and can speed up future technology development by years,” says Asenov, “it can also help fabless companies to make the right technology choices for their products in the diversified-technology world where NWT technology will compete with conventional bulk, FDSOI and FinFET CMOS. Once the choice is made the technology can be optimised for the requirements of data farms, laptops, tablets, smart phones, wearable electronic devices and the IoT as a whole.”

Asenov remains a fan of FD-SOI. “I’m a believer,” he says, “Samsung is manufacturing in FD-SOI for ST and will open it to mass production. I have seen FD-SOI. products from Sony and Globalfoundries. FD-SOI is good for IoT. At 14nm, FD-SOI is much cheaper.”